ALINX FL9295 (01) PDF DOCUMENT

The ALINX FL9295 is a 4-channel GMSL2 camera acquisition and video simulation injection module. It utilizes one MAX96712 chip for 4-channel video decoding input and four MAX9295A chips for video coding output. The chips are automotive-grade and support both first-generation GMSL1 and second-generation GMSL2 standards with serial speeds of 3Gbps and 6Gbps.

The module features a 4-in-1 FAKRA coaxial connector for the video interface. Its 4-LANE MIPI signals connect to an ALINX FPGA development board via a standard LPC FMC interface (VITA 57.1), with each lane supporting up to 2.5Gbps for video image conversion and transmission.

Camera Input/Output:

The module supports 4-channel GMSL1/2 camera input and output.

Input: Supports 4-channel camera, up to 8MP 30-frame resolution camera.

Output: Supports 4-channel video output, supporting 2MP/4MP at 60 frames, or 8MP at 30 frames.

Cable Length:

Up to 40m (3Gbps) in GMSL1 mode.

Up to 20 meters (6Gbps) in GMSL2 mode.

Connector:

Uses Amphenol Z Code FAKRA AG coaxial connectors.

Input and Output Image Format:

Supports RAW8/10/12/14/16/20, RGB565/666/888, and YUV422 8/10bit video image formats, which can be configured using I2C.

FMC Interface:

Features a Standard LPC connector.

The overall dimensions of the ALINX FL9295 module are 76.50mm by 69.00mm.

The ALINX FL9295 module manages video input and output through a series of specialized chips connected to an FMC interface.

For Video Input (Camera Acquisition): Video data from cameras enters through the FAKRA connectors (J1) as COAXA-COAXD signals. These signals are processed by the MAX96712 deserializer chip. The MAX96712 then converts the GMSL video data into a 4-lane MIPI signal, which is sent to the FPGA via the FMC connector (J2). Power over Coax (PoC) is managed by a dedicated POC chip.

For Video Output (Video Simulation): The FPGA sends four separate 4-lane MIPI signals to the module via the FMC connector. Each MIPI signal is routed to one of the four MAX9295A serializer chips. Each MAX9295A chip converts its respective MIPI signal into a GMSL signal (COAXA, COAXB, COAXC, COAXD) and sends it out through the FAKRA connectors (J1/J3).

All chips (MAX96712, MAX9295A, POC chip) are configurable via I2C from the FPGA.

The following table details the pin assignment of the ALINX FL9295 FMC LPC interface when connected to a Z7-P development board. Power and GND signals are not listed.

Currently, the ALINX FL9295 module can only be adapted to Z7-P and Z19-P development boards. To install, align the FMC connector on the ALINX FL9295 with the corresponding FMC connector on the Z7-P or Z19-P development board and press them firmly together until fully seated.

To display real-time video from four cameras, follow this setup:

1. Install the ALINX FL9295 module onto a compatible development board, such as the Z7-P.

2. Connect a 4-channel on-board camera (e.g., 2 million pixels) to the FAKRA inputs on the ALINX FL9295 module.

3. Connect the DisplayPort (DP) interface of the development board to a 4K DP display.

4. Power on the system. The images acquired by the 4-channel video will be displayed in real-time on the DP display, typically in a quad-view format.

A loopback test verifies both the output and input functionality of the module. To perform this test, you connect the output channels back to the input channels.

Setup:

1. Install the ALINX FL9295 onto a compatible development board (e.g., Z7-P).

2. Using coaxial cables with FAKRA connectors, physically loop the output video signals from the MAX9295A chips back into the input video ports of the MAX96712 chip on the same module.

3. Connect the DP interface of the development board to a DP display.

Procedure:

1. The FPGA on the development board generates a test image (e.g., color bars, checkerboard pattern).

2. The FPGA outputs this test image via MIPI signals to the MAX9295A serializer chips.

3. The MAX9295A chips encode the MIPI signals into GMSL format and send them out through the FAKRA connectors.

4. The looped coaxial cables route these GMSL signals back into the FAKRA inputs of the module.

5. The MAX96712 chip receives the GMSL signals, decodes them, and outputs them as MIPI signals back to the FPGA.

6. The FPGA processes the received image and sends it to the DP display.

7. The test image generated by the FPGA should be visible on the DP display, confirming that the entire signal path (FPGA -> MAX9295A -> GMSL loop -> MAX96712 -> FPGA) is working correctly.